3M™ Trizact™ 研磨墊在半導體製造過程中呈現高度一致的性能和研磨效率。
隨著像是物聯網、智慧城市、行動通訊、邊緣運算等驅使世界的趨勢,半導體日漸增長地記憶體和速度的需求。瓶頸來自於半導體製造過程中的化學機械平坦化(CMP)從需求到良率地持續提升,使得半導體廠無法容忍元件可靠度變異。
3M利用3M™ Trizact™ 研磨墊重新定義研磨墊產品,確保半導體化學機械平坦化製程的穩定性和一致性。
3M™ Trizact™ 研磨墊平整器結合了3M在造模、表面改質和微複製方面的專業技術,為先進節點的半導體製造提供了化學機械拋光的創新研磨墊。
3M™ Trizact™ 研磨墊採用我們專有的微複製製程,為了您所需要的化學機械平坦化效能所設計,最後呈現良好一致性的研磨墊。
一致與可重複的化學機械平坦化效能可提升晶圓良率。3M™ Trizact™ 研磨墊有助於提升平坦化效率、降低晶圓缺陷並提升生產力與產量。
我們專有的顯微複製技術提供了較長研磨墊壽命,不須使用鑽石研磨墊修整器。
3M™ Trizact™ 研磨墊使用3M核心平台中的「顯微複製技術」。此技術讓我們能精準的雕刻微小特徵,達成極高的表面一致性。此技術最初是因投影機的光線調控特性所誕生,現已延伸至3M成千上萬的產品。
Technical paper published by The Electrochemical Society (ECS), August 2016
Within-die non-uniformity (WIDNU) determined by gate height range among 3 different devices, and by the range in dielectric thickness on top of gate (i.e., TS dielectric) between 3 different devices. One center die, one middle die, and one edge die from wafers polished with POR and MR pads are submitted for cross-sectional TEM analysis, from which gate height and dielectric thickness measurements are taken.
Authors: Wei-Tsu Tseng, Kaushik Mohan, Ricky Hull, James Hagan, Connie Truong, Duy K. Lehuu, and David Muradian
A microreplicated (MR) pad with regulated long-range order surface pore-asperity patterns is used for the buff polish step in a 3-platen W-CMP process for 14 nm replacement metal gate (RMG) and trench salicide (TS) planarization. This new pad requires no diamond tip conditioner and can last up to 2000 wafer passes with highly repeatable removal rates, while maintaining low and consistent defects and within-wafer uniformity. The MR pad also provides unique benefits of mitigating within-die non-uniformity as demonstrated by gate electrical conductance tests and confirmed by physical thickness measurement through cross-sectional TEM.
In addition, topography-driven defects are reduced significantly. The mechanisms responsible for the unique performance of MR pads will be elucidated and the significance of this new CMP pad technology will be discussed.
Technical paper published by Institute of Electrical and Electronics Engineers (IEEE), May 2017
Authors: Wei-Tsu Tseng, Changhong Wu, James Hagan, Yanni Wang, Hong Lin, Ja-Hyung Han, Dinesh Koli
With advanced nodes selecting cobalt for more and more layers, it is becoming a greater challenge to maintain within-die non-uniformity for control or gate height and trench height. Read more about the 3M™ Trizact™ CMP Pad for Cobalt buff CMP defectivity and topography performance presented by Global Foundries at the 2017 IEEE International Interconnect Technology Conference (IITC).
查看更多用於CMP和表面處理材料的3M解決方案,可幫助增加生產力並提升良率,和高質量的製程表現。
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