3M™ Trizact™ 研磨墊
3M™ Trizact™ 研磨墊在半導體製造過程中呈現高度一致的性能和研磨效率。
主要設計讓化學機械平坦化製程 (CMP)都能達到可預測、穩定和一致的效能。
隨著像是物聯網、智慧城市、行動通訊、邊緣運算等驅使世界的趨勢，半導體日漸增長地記憶體和速度的需求。瓶頸來自於半導體製造過程中的化學機械平坦化(CMP)從需求到良率地持續提升，使得半導體廠無法容忍元件可靠度變異。
3M利用3M™ Trizact™ 研磨墊重新定義研磨墊產品，確保半導體化學機械平坦化製程的穩定性和一致性。
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先進節點的高級效能
3M™ Trizact™ 研磨墊平整器結合了3M在造模、表面改質和微複製方面的專業技術，為先進節點的半導體製造提供了化學機械拋光的創新研磨墊。
- 利用設計精準的三維微複製粗糙突起和孔隙，來界定研磨墊的紋理，並幫助確保研磨墊對研磨墊效能的一致性 —達到先進節點化學機械平坦化流程的要求。
- 粗糙突起和孔隙被安排於獨立的隔間，來確保晶片上的壓力一致。
- 我們高度可控的微複製製程可完成可複製且可調諧的CMP研磨墊。
降低變異性，提高重複性 — 改善晶圓良率
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一致性
3M™ Trizact™ 研磨墊採用我們專有的微複製製程，為了您所需要的化學機械平坦化效能所設計，最後呈現良好一致性的研磨墊。
- 機械平坦化中的一致性
- 每片一致的表面圖案
- 研磨墊使用期間達到研磨使用過程中的穩定性
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提升良率
一致與可重複的化學機械平坦化效能可提升晶圓良率。3M™ Trizact™ 研磨墊有助於提升平坦化效率、降低晶圓缺陷並提升生產力與產量。
- 提升平坦化效率來以符合CMP先進製程節點的需求
- 降低晶圓淺碟型與腐蝕型凹陷現象
- 減少研磨墊產生的碎屑，可降低晶圓缺陷
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減少CMP耗材
我們專有的顯微複製技術提供了較長研磨墊壽命，不須使用鑽石研磨墊修整器。
- 降低金屬污染的風險
- 降低晶圓生產成本
- 延長研磨墊壽命，增加機台使用時間
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3M™ Trizact™ 研磨墊的精準設計三維顯微複製表面粗糙特徵。顯微複製技術—微觀世界的一致性
3M™ Trizact™ 研磨墊使用3M核心平台中的「顯微複製技術」。此技術讓我們能精準的雕刻微小特徵，達成極高的表面一致性。此技術最初是因投影機的光線調控特性所誕生，現已延伸至3M成千上萬的產品。
Technical paper published by The Electrochemical Society (ECS), August 2016
A Microreplicated Pad for Tungsten Chemical-Mechanical Planarization
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Within-die non-uniformity (WIDNU) determined by gate height range among 3 different devices, and by the range in dielectric thickness on top of gate (i.e., TS dielectric) between 3 different devices. One center die, one middle die, and one edge die from wafers polished with POR and MR pads are submitted for cross-sectional TEM analysis, from which gate height and dielectric thickness measurements are taken.
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Authors: Wei-Tsu Tseng, Kaushik Mohan, Ricky Hull, James Hagan, Connie Truong, Duy K. Lehuu, and David Muradian
A microreplicated (MR) pad with regulated long-range order surface pore-asperity patterns is used for the buff polish step in a 3-platen W-CMP process for 14 nm replacement metal gate (RMG) and trench salicide (TS) planarization. This new pad requires no diamond tip conditioner and can last up to 2000 wafer passes with highly repeatable removal rates, while maintaining low and consistent defects and within-wafer uniformity. The MR pad also provides unique benefits of mitigating within-die non-uniformity as demonstrated by gate electrical conductance tests and confirmed by physical thickness measurement through cross-sectional TEM.
In addition, topography-driven defects are reduced significantly. The mechanisms responsible for the unique performance of MR pads will be elucidated and the significance of this new CMP pad technology will be discussed.
Technical paper published by Institute of Electrical and Electronics Engineers (IEEE), May 2017
Microreplicated CMP Pad for RMG and MOL Metallization
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Innovative groove design of 3M™ Trizact™ CMP pad – SEM image at 35x magnificationAuthors: Wei-Tsu Tseng, Changhong Wu, James Hagan, Yanni Wang, Hong Lin, Ja-Hyung Han, Dinesh Koli
With advanced nodes selecting cobalt for more and more layers, it is becoming a greater challenge to maintain within-die non-uniformity for control or gate height and trench height. Read more about the 3M™ Trizact™ CMP Pad for Cobalt buff CMP defectivity and topography performance presented by Global Foundries at the 2017 IEEE International Interconnect Technology Conference (IITC).
了解更多3M半導體產業解決方案
查看更多用於CMP和表面處理材料的3M解決方案，可幫助增加生產力並提升良率，和高質量的製程表現。
感謝您對於3M半導體產業解決方案的興趣，我們將盡快回覆您的詢問。